sp1: mu: Add memory mapped I/O helpers

Signed-off-by: Chloe M. <chloe@mirocom.org>

README

@@ -5,7 +5,7 @@ their work (or fun! >:3) done while having their machine resources managed clean
 scenes. SPx is architected by a fluffy kitty cat who likes eating bugs and mice and RATS NOM
 NOM NOM !!!! This kitty will protect your wittle den, don't worry critter!
 
--- Confidentiality of implementation --
+-- Open source --
 
-This repository and its sources as of Thu Apr 16 is CONFIDENTIAL and PROPRIETARY.
-Unauthorized distribution or modification is strictly prohibited.
+This system software has been open sourced, all confidentiality notices have been preserved
+for historical purposes.

tools/bootstrap.sh

@@ -34,7 +34,7 @@ check_deps() {
 #
 get_toolchain() {
     if [ ! -d var/cc/toolchain ]; then
-        git clone https://git.mirocom.org/Mirocom/mirocom-toolchain --depth=1 var/cc/toolchain
+        git clone https://git.mirocom.org/chloe/mirocom-toolchain --depth=1 var/cc/toolchain
         cd var/cc/toolchain
         tar -xzvf toolchain.tar.gz
         mv public/* .; rm -rf public/

usr/src/sp1/amd64/io/irqchip.c

@@ -16,6 +16,7 @@
 #include <machine/irqchip.h>
 #include <io/acpi/acpi.h>
 #include <io/acpi/tables.h>
+#include <mm/vm.h>
 
 #define pr_trace(fmt, ...) \
     printf("irqchip: " fmt, ##__VA_ARGS__)
@@ -23,6 +24,40 @@
 /* Online capable */
 #define LAPIC_ONLCAP BIT(1)
 
+/* I/O APIC */
+static struct irqchip ioapic_list[MAX_IOAPIC];
+static size_t ioapic_count = 0;
+
+/* Local APIC */
+static struct irqchip lapic_list[MAX_LAPIC];
+static size_t lapic_count = 0;
+
+/*
+ * Add a Local APIC descriptor
+ */
+static inline void
+irqchip_lapic_append(const struct irqchip *irqchip)
+{
+    if (lapic_count >= MAX_LAPIC) {
+        return;
+    }
+
+    lapic_list[lapic_count++] = *irqchip;
+}
+
+/*
+ * Add an I/O APIC descriptor
+ */
+static inline void
+irqchip_ioapic_append(const struct irqchip *irqchip)
+{
+    if (ioapic_count >= MAX_IOAPIC) {
+        return;
+    }
+
+    ioapic_list[ioapic_count++] = *irqchip;
+}
+
 /*
  * Print information about a Local APIC unit
  */
@@ -63,6 +98,7 @@ irqchip_print_ioapic(struct ioapic *ioapic)
 status_t
 md_irqchip_init(void)
 {
+    struct irqchip chip;
     struct acpi_madt *madt;
     struct local_apic *lapic;
     struct ioapic *ioapic;
@@ -84,13 +120,41 @@ md_irqchip_init(void)
         case APIC_TYPE_LOCAL_APIC:
             lapic = (struct local_apic *)hdr;
             irqchip_print_lapic(lapic);
+
+            chip.mmio = pma_to_vma(madt->lapic_addr);
+            chip.apic_id = lapic->apic_id;
+            irqchip_lapic_append(&chip);
             break;
         case APIC_TYPE_IO_APIC:
             ioapic = (struct ioapic *)hdr;
             irqchip_print_ioapic(ioapic);
+
+            chip.mmio = pma_to_vma(ioapic->ioapic_addr);
+            chip.apic_id = ioapic->ioapic_id;
+            irqchip_lapic_append(&chip);
             break;
         }
 
         cur += hdr->length;
     }
 }
+
+struct irqchip *
+md_ioapic_index(size_t index)
+{
+    if (index >= ioapic_count) {
+        return NULL;
+    }
+
+    return &ioapic_list[index];
+}
+
+struct irqchip *
+md_lapic_index(size_t index)
+{
+    if (index >= lapic_count) {
+        return NULL;
+    }
+
+    return &lapic_list[index];
+}

usr/src/sp1/head/amd64/irqchip.h

@@ -14,9 +14,51 @@
 
 #include <sys/status.h>
 
+#define MAX_IOAPIC 8
+#define MAX_LAPIC 64
+
+/*
+ * @IRQCHIP_NONE: This IRQ chip has no type
+ * @IRQCHIP_LAPIC: This IRQ chip is a Local APIC
+ * @IRQCHIP_IOAPIC: This IRQ chip is an I/O APIC
+ */
+typedef enum {
+    IRQCHIP_NONE,
+    IRQCHIP_LAPIC,
+    IRQCHIP_IOAPIC
+} irqchip_type_t;
+
+/*
+ * Represents a platform interrupt controller
+ * chip
+ *
+ * @type:       IRQ chip type
+ * @apic_id:    APIC ID
+ * @mmio:       Memory mapped I/O address
+ */
+struct irqchip {
+    irqchip_type_t type;
+    uint8_t apic_id;
+    void *mmio;
+};
+
 /*
  * Initialize platform interrupt controller chips
  */
 status_t md_irqchip_init(void);
 
+/*
+ * Obtain an I/O APIC descriptor by index
+ *
+ * @index: Index of entry to obtain
+ */
+struct irqchip *md_ioapic_index(size_t index);
+
+/*
+ * Obtain an Local APIC descriptor by index
+ *
+ * @index: Index of entry to obtain
+ */
+struct irqchip *md_lapic_index(size_t index);
+
 #endif  /* !_MACHINE_IRQCHIP_H_ */

usr/src/sp1/head/mm/vm.h

@@ -39,7 +39,7 @@ struct vm_map {
  * and vice versa.
  */
 #define pma_to_vma(pma) \
-    PTR_OFFSET((void *)pma, bpt_kload_base())
+    PTR_OFFSET((void *)((uintptr_t)pma), bpt_kload_base())
 #define vma_to_pma(vma) \
     (uintptr_t)PTR_NOFFSET(vma, bpt_kload_base())
 

usr/src/sp1/head/mu/mmio.h

@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2026, Mirocom Laboratories
+ * All rights reserved.
+ *
+ * The following sources are CONFIDENTIAL and PROPRIETARY
+ * property of Mirocom Laboratories. Unauthorized copying,
+ * use, distribution or modification of this file, in whole
+ * and in part, is strictly prohibited without the prior written
+ * consent from Mirocom Laboratories.
+ */
+
+#ifndef _MU_MMIO_H_
+#define _MU_MMIO_H_ 1
+
+#include <sys/cdefs.h>
+
+/* Builds mmio_write<n> functions */
+#define _MMIO_WRITE_BUILDER(NAME, TYPE)     \
+    static inline void                      \
+    mmio_##NAME(TYPE *ptr, TYPE val)        \
+    {                                       \
+        __barrier();                        \
+        *(volatile TYPE *)ptr = val;        \
+    }
+
+/* Builds mmio_read<n> functions */
+#define _MMIO_READ_BUILDER(NAME, TYPE)      \
+    static inline TYPE                      \
+    mmio_##NAME(TYPE *ptr)                  \
+    {                                       \
+        __barrier();                        \
+        return *(volatile TYPE *)ptr;       \
+    }
+
+/* mmio_write<n> */
+_MMIO_WRITE_BUILDER(write8, uint8_t);
+_MMIO_WRITE_BUILDER(write16, uint16_t);
+_MMIO_WRITE_BUILDER(write32, uint32_t);
+#if __SIZEOF_SIZE_T__ == 8
+_MMIO_WRITE_BUILDER(write64, uint64_t);
+#endif
+
+/* Builds mmio_read<n> functions */
+_MMIO_READ_BUILDER(read8, uint8_t);
+_MMIO_READ_BUILDER(read16, uint16_t);
+_MMIO_READ_BUILDER(read32, uint32_t);
+#if __SIZEOF_SIZE_T__ == 8
+_MMIO_READ_BUILDER(read64, uint64_t);
+#endif
+
+#endif  /* !_MU_MMIO_H_ */