Since on UefiPayload the full PCI enumeration isn't run, the light
enumeration won't find Option ROMs. The introduced PciPlatform
driver relies on completed PCI enumeration and assumes that all
ROM bars have been properly assigned a free MMIO window.
Installs the gPciPlatformProtocol to scan for Option ROMs during
PCI enumeration light and copies found Option ROMs to runtime allocated
buffers. Only for work devices that have a ROMBAR, but doesn't for
devices that need a VBIOS loaded from SPI flash.
TEST: QEMU can enumerate Option ROMs on VGA and NIC on UefiPayloadPkg.
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
The entrypoint module should do this programmatically using resources
passed by the bootloader. Under UPL, bootloaders are expected to pass
such ranges in the FDT.
Signed-off-by: Benjamin Doron <benjamin.doron@9elements.com>
When register a root SMI handler, it is expected to use windows calling
convention for the SMI handler. This patch adds missing EFIAPI for the
SMI handler SmmSwDispatcher to avoid potential issue from Linux build.
Signed-off-by: Guo Dong <guo.dong@intel.com>
The Universal Graphics Adapter (UGA) is a graphic abstraction.
The UGA I/O and Draw protocols are deprecated since UEFI 2.0 was
introduced. Cf. the UEFI spec v2.9:
"Appendix L - EFI 1.10 Protocol Changes and Deprecation List"
section L.2 "Deprecated Protocols"
Remove the UGA support.
Signed-off-by: GuoMinJ <newexplorerj@gmail.com>
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
UefiPayloadPkg has copied the MdeModulePkg DxeIpl behavior to
create a memory allocation HOB for page 0. That is being changed
(see that commit for details), so also remove it here.
Signed-off-by: Oliver Smith-Denny <osde@microsoft.com>
Introduce AArch64 architecture support in BlSupportDxe. Translation
table would be created based on the memory maps, which is provided
by bootloader, in case MMU is disabled when execution is handed
over to Universal Payload.
Signed-off-by: Ajan Zhong <ajan.zhong@newfw.com>
Move ArmMmuLib from ArmPkg to UefiCpuPkg for easy maintaining.
Continuous-integration-options: PatchCheck.ignore-multi-package
Signed-off-by: Ajan Zhong <ajan.zhong@newfw.com>
fix SPI prefetch and cache disable value and define SRC bitfield position
correct register setting in SaveAndDisableSpiPrefetchCache
Signed-off-by: Kevin Tsai <kevin.tsai@intel.com>
Commit 8040fdbb8b (MdePkg: consistently use "Property" in BaseFdtLib)
got a bit carried away and confused around how libfdt contains both
getprop and get_property functions, which operate quite differently;
the getprop variant returns a pointer to the value of the property,
whereas the get_property returns a pointer to the fdt_property
structure.
Untangle this, including fixing up affected existing in-tree users, and
adding the previously not exported FdtGetProp wrapper on fdt_getprop.
Continuous-integration-options: PatchCheck.ignore-multi-package
Signed-off-by: Leif Lindholm <leif.lindholm@oss.qualcomm.com>
MemoryTypeInformation HOB was built in FD and FIT image format UEFI payload.
But this HOB was not built in ELF image format UEFI payload. Adding this HOB
for ELF image format to keep payload consistent in different image format.
When this HOB is missing, DXE/SMM driver might be dispatched above 4GB and
MemoryType information HOB assists GCD with defragmenting the memory map.
Signed-off-by: Guo Dong <guo.dong@intel.com>
when SMM_SUPPORT is enabled, a build failure was seen since two SMM
libraries are missing. Just add them in the DSC file to fix it.
Signed-off-by: Guo Dong <guo.dong@intel.com>
This commit is to add two new APIs in UefiPayloadPkg
DxeHobLib and PayloadEntryHobLib:
1.The GetNextMemoryAllocationGuidHob () returns the next
instance of the Memory Allocation HOB with the matched
GUID from a starting HOB pointer.
2.The TagMemoryAllocationHobWithGuid () searchs the HOB
list for the Memory Allocation HOB with a matching base
address and set the Name GUID. Then the instance of the
tagged Memory Allocation HOB with matched base address is
returned.
Signed-off-by: Dun Tan <dun.tan@intel.com>
AArch64 no longer uses PcdVFPEnabled, so make the definition ARM-specific
and stop explicitly setting it for AArch64 platforms.
Continuous-integration-options: PatchCheck.ignore-multi-package
Signed-off-by: Leif Lindholm <leif.lindholm@oss.qualcomm.com>
As an implementation of an industry specification-defined interface,
ArmSmcLib is more appropriately placed in MdePkg.
This update relocates both the header definition and the implementation
of ArmSmcLib to MdePkg, thereby supporting the monitor call primitives
for all other packages that depend on this interface.
Continuous-integration-options: PatchCheck.ignore-multi-package
Signed-off-by: Kun Qin <kun.qin@microsoft.com>
This adds support for FVB in order to support a platform-independent
non-volatile variable store on UefiPayloadPkg. The variable store makes
use of the SmmStoreLib to provide an unauthenticated variable store.
Since commit bc744f5893fc4d53275ed26dd8d968011c6a09c1 coreboot supports
the SMMSTORE v2 feature. It implements an SMI handler that is able to
write, read and erase pages in the boot media (SPI flash).
The communication is done using a fixed communication buffer that is
allocated in CBMEM. The existence of this optional feature is advertised
by a coreboot table. When the SMMSTORE feature is not available, the
variable emulation is used by setting PcdEmuVariableNvModeEnable to
TRUE.
The DXE component provides runtime services and takes care of virtual to
physical mapping the communication buffers between SMM and OS.
The contents of the variable store can be accessed and modified by any
privileged application. As authentication is done by runtime services
only the store shouldn't be used to store authenticated variables.
Tested on Linux and Windows on a variety of real hardware.
This can also be tested in QEMU starting with coreboot 24.12 using
qemu-q35 board.
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Implement all of the FVB protocol functions on top of the SmmStore
as a library. The library consumes the introduced
gEfiSmmStoreInfoHobGuid.
The SMI handler uses a fixed communication buffer in reserved DRAM.
To initiate a transaction you must write to the I/O APM_CNT port.
Tests on Intel(R) Xeon(R) E-2288G CPU @ 3.70G showed that the SMI isn't
triggered with a probability of 1:40 of all cases when called in a tight
loop. The CPU continues running and the SMI is triggered asynchronously
a few clock cycles later. coreboot only handles synchronous APM request
and does nothing on asynchronous APM triggers.
As there's no livesign from SMM it's impossible to tell if the handler
has run. Just wait a bit and try again to trigger a synchronous SMI.
Tests confirmed that out of 5 million tries the SMI is now always
handled.
When a synchronous SMI happens with the correct write to the APM_CNT
port, the ebx register is checked first that it doesn't point to SMRAM.
If it doesn't it's used to read in the arguments that define an SmmStore
transaction.
The SMI handler will only operate on a predefined and memory mapped
region in the boot media.
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Add a new InfoHob that contains the SmmStore information passed from
coreboot tables when the SMMSTOREV2 feature is enabled.
This will be used to implement the FVB on top of the SMI installed by
coreboot.
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Since commit bc744f5893fc4d53275ed26dd8d968011c6a09c1 coreboot supports
the SMMSTORE v2 feature. It implements an SMI handler that is able to
write, read and erase pages in the boot media (SPI flash).
The existence of this optional feature is advertised by a coreboot
table.
Add the tag and header definition to be able to parse the table.
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
OVMF SmbiosVersionLib applies to QEMU SMBIOS only, it does not
work on Bare Metal platform. Drop SmbiosVersionLib dependency
for SmbiosDxe on AArch64 architecture.
Signed-off-by: Ajan Zhong <ajan.zhong@newfw.com>
Recent AMD platforms reserve parts of the lower DRAM where UefiPayload is
being loaded to and since UefiPayloadEntry doesn't care, it uses the reserved
memory for HOB and memory allocation.
The bootloader cannot prevent this, as it can only place the UEFI FV in
usable DRAM, but it has no control over EfiBootService memory allocations.
This issue prevents boot on those platforms without any specific error message.
It's not vendor specific and can happen on every platform.
Add the same logic as used on UniversalPayload and do the following:
- Walk bootloader provided memory information
- Skip everything that's not marked as usable DRAM
- Align entries to 1MiB boundary
- Don't use memory above 4GiB on x86_32
- Skip memory ranges too small
- Don't use memory currently occupied by the UEFI FV itself
Once a useable memory range is found pass it to HobConstructor().
TEST: Fixes boot on AMD/glinda, that reserved memory at 2000000h.
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
When FDT based DTB is parsed, variables mPciRootBridgeInfo and
mUplPciSegmentInfoHob are always dereferenced. If there is no PCI
RB Bridge info or RB Segment info provided in FDT, it leads to
NULL pointer dereferenced.
To address this issue, parse PCI RB and Segment information only
when they are available at FDT. If they are unavailable, skip it
and allow the PciBusDxe and PciHostBridgeDxe to handle them.
Signed-off-by: Ajan Zhong <ajan.zhong@newfw.com>
Create a new PlatformBuild.py that can be called by stuart_build.
UniversalPayloadBuild.py is consumed by new script to maintain backward
compatibility and eliminate duplicate build steps.
Supported builds:
1. UEFI package build: directly call BaseTools build for EFI bin
2. UPL ELF/FIT build: call UniversalPayloadBuild.py
3. (new) UPL ELF - stuart build: follow stuart build steps to call
PlatformBuild.py (edk2toolext is mandatory)
Signed-off-by: Gua Guo <gua.guo@intel.com>
Add new option "--add_cc_flag" to append CC compilation flags when build
Payload. With this option, user can append specified build options in
build script.
Usage example to add more CC flags:
python UefiPayloadPkg/UniversalPayloadBuild.py -t GCC5 -b DEBUG --Fit \
--add_cc_flag=-mno-sse --add_cc_flag=-mno-mmx
Signed-off-by: Ajan Zhong <ajan.zhong@newfw.com>
Add new macro HAND_OFF_FDT_ENABLE to control status of PcdHandOffFdtEnable.
With this macro enabled in build script, PcdHandOffFdtEnable can be enabled
without editing in souce code.
Default vale of HAND_OFF_FDT_ENABLE is FALSE.
Signed-off-by: Ajan Zhong <ajan.zhong@newfw.com>
Add basic support for FIT image on the AARCH64 architecture, reuse
exsitting DSC and FDF files for IA32, X64 and AARCH64 architectures.
Introduce new PCD: PcdUseUniversalPayloadSerialPort to indicate
which serial port module is used due to some serial port parameters
are fixed for ARM SoC and Platform.
Please use following command to build AARCH64 UPL FIT image:
"
export GCC5_AARCH64_PREFIX=aarch64-linux-gnu-
python UefiPayloadPkg/UniversalPayloadBuild.py -a AARCH64
-t GCC5 -b DEBUG --Fit
"
Signed-off-by: Amos Bu <amos.bu@newfw.com>
Signed-off-by: Ajan Zhong <ajan.zhong@newfw.com>
UefiPayloadEntry utilizes CPUID 0x80000008 leaf to retrieve the Processor's
Physical Address size for X86 architecture. To enable support for multiple
architectures, replace the direct implementation with an architecture-level
function provided by the UefiCpuPkg library, abstracting the underlying details.
Signed-off-by: Ajan Zhong <ajan.zhong@newfw.com>
This patch moves `PcdPlatformBootTimeOut` from `[PcdsDynamicExDefault]`
to `[PcdsDynamicHii]`, allowing the boot timeout to be configured through
HII, rather than being a compile-time setting.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Commit efbf5ed moves StackCheckLibStaticInit to StackCheckLib,
and each SEC module has a dependency on StackCheckLib now.
Add StackCheckLib in FitUniversalPayloadEntry.inf to fix build
issue.
Signed-off-by: Ajan Zhong <ajan.zhong@newfw.com>
This commit oves StackCheckLib from a NULL lib to an instance of
StackCheckLib. This requires every entry point to add a library
dependency on StackCheckLib. It also requires every SEC module
to have a dependency on StackCheckLib because there is no
standard SEC entry point.
It allows for greater flexibility for a platform to apply stack
cookies and simplifies DSC logic.
Continuous-integration-options: PatchCheck.ignore-multi-package
Signed-off-by: Oliver Smith-Denny <osde@microsoft.com>
With the latest GccBase.lds combining with CLANG build, there is no
need to enforce 4KB alignment of in UPL CLANGDWARF build.
This reverts commit b3bfb8f22d.
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Original ELF segment/section syncup process having layout assumption
which has caused build failure when layout changing.
New process will parse both existing segments and sections firstly to
support different layout.
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
After commit aca75d3 the PayloadEntry ELF header will miss dynamic
section which caused PEI_ASSERT in PayloadLoader rebasing code.
This commit adding common-page-size=0x1000 to CLANGDWARF_DLINK_FLAGS
to overcome the ELF header generation issue.
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Merge the PCI root bridge with the same segment address within one.
PciSegment element.
UefiPayloadPkg/Library/PciSegmentInfoLibAcpiBoardInfo/PciSegmentInfoLibAcpiBoardInfo.c
Signed-off-by: Linus Liu <linus.liu@intel.com>
In platform which support ACPI 2.0 only, the base address of ACPI region
is not page aligned. This unalinged base address leads to failure at
BuildMemoryAllocationHob when parsing ACPI node in FdtParserLib, before
building gUniversalPayloadAcpiTableGuid GUID HOB.
Align base address of ACPI region down to EFI_PAGE_SIZE to make sure
base address always aligned.
Signed-off-by: Ajan Zhong <ajan.zhong@newfw.com>
PixelsPerScanLine is required in some UEFI capable OS distribution.
To align with simple-framebuffer definition in kernel Documentation:
devicetree/bindings/display/simple-framebuffer.txt, no property node
will be introduced for PixelsPerScanLine.
Set value of PixelsPerScanLine to HorizontalResolution, as they are
identical in most cases.
Signed-off-by: Ajan Zhong <ajan.zhong@newfw.com>
Current implementation only supports serial port sub-node under
PCI root bridge node.
This enhancement support serial port node regardless it is under
root node or PCI root bridge node using a single FDT passing function.
Signed-off-by: Guo Dong <guo.dong@intel.com>
According to ACPI Specification, 64 bit physical address of the XSDT
provides indentical functionality to the RSDT but accommodates physical
address of description headers that are larger than 32 bits.
In this case physical address of XSDT table is 64 bit aligned, however
size of ACPI description tabled header is not 64 bit aligned. It leads
to the entry of other description headers are not 64 bit aligned. In
AARCH64 architecture, deference non-aligned 64 bit address to fetch
64-bit data will trigger Alignment fault. Use ReadUnaligned64 method
to fix this unaligned data access issue.
Signed-off-by: Ajan Zhong <ajan.zhong@newfw.com>
If alignment check is enabled in AARCH64 platform, FDT parser might
dereference non-aligned 64-bit address to fetch 64-bit data.
Use unaligned data read to avoid triggering unaligned data access.
Signed-off-by: Ajan Zhong <ajan.zhong@newfw.com>
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4873
Currently the function does not cover the 5 level paging case. it will
casued pagetable protection region set incorrectly. This patch do the
enhancemant and with the patch protection region has been set correctly.
Signed-off-by: Ning Feng <ning.feng@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Now that the ResetVectors are USER_DEFINED modules, they will not
be linked against StackCheckLibNull, which were the only modules
causing issues. So, we can now remove the kludge we had before
and the requirement for every DSC to include StackCheckLibNull
for SEC modules and just apply StackCheckLibNull globally.
This also changes every DSC to drop the SEC definition of
StackCheckLibNull.
Continuous-integration-options: PatchCheck.ignore-multi-package
Signed-off-by: Oliver Smith-Denny <osde@linux.microsoft.com>
There are couples of gUniversalPayloadAcpiTableGuid in
payload , only build one
gUniversalPayloadAcpiTableGuid hob and acpi memory hob.
when the reserved memory address matched the rsdp.
Signed-off-by: Linus Liu <linus.liu@intel.com>
