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UefiPayloadPkg: fix SPI prefetch and cache disable setting

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fix SPI prefetch and cache disable value and define SRC bitfield position
correct register setting in SaveAndDisableSpiPrefetchCache

Signed-off-by: Kevin Tsai <kevin.tsai@intel.com>
This commit is contained in:
Kevin Tsai
2025-06-03 12:10:26 -07:00
committed by mergify[bot]
parent 8810c3b270
commit 45010d2812
2 changed files with 5 additions and 4 deletions
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6
UefiPayloadPkg/Library/SpiFlashLib/PchSpi.c
View File

@@ -144,10 +144,10 @@ SaveAndDisableSpiPrefetchCache (
BiosCtlSave = MmioRead8 (PchSpiBase + R_SPI_BCR) & B_SPI_BCR_SRC;
MmioAndThenOr32 (
MmioAndThenOr8 (
PchSpiBase + R_SPI_BCR, \
(UINT32)(~B_SPI_BCR_SRC), \
(UINT32)(V_SPI_BCR_SRC_PREF_DIS_CACHE_DIS << B_SPI_BCR_SRC)
(UINT8)(~B_SPI_BCR_SRC), \
(UINT8)(V_SPI_BCR_SRC_PREF_DIS_CACHE_DIS << N_SPI_BCR_SRC)
);
return BiosCtlSave;

3
UefiPayloadPkg/Library/SpiFlashLib/RegsSpi.h
View File

@@ -13,7 +13,8 @@
#define B_SPI_BAR0_MASK 0x0FFF
#define R_SPI_BCR 0xDC ///< BIOS Control Register
#define B_SPI_BCR_SRC (BIT3 | BIT2) ///< SPI Read Configuration (SRC)
#define V_SPI_BCR_SRC_PREF_DIS_CACHE_DIS 0x04 ///< Prefetch Disable, Cache Disable
#define N_SPI_BCR_SRC 2 ///< SPI Read Configuration bit position
#define V_SPI_BCR_SRC_PREF_DIS_CACHE_DIS 0x01 ///< Prefetch Disable, Cache Disable
#define B_SPI_BCR_SYNC_SS BIT8
#define B_SPI_BCR_BIOSWE BIT0 ///< Write Protect Disable (WPD)