ArmPlatformPkg/Sec: Remove EL1 timer setup when booting at EL2

Even though the UEFI spec mentions that the EL1PCTEN and EL1PCEN bits in
CNTHCTL_EL2 must be set, this is not a requirement that applies to the
UEFI implementation, but a requirement that applies to the firmware
running at EL2 in cases where UEFI executes at EL1. (Note that the same
paragraphs mentions that CNTFRQ must be programmed with the timer
frequency, and this is only permitted at EL3).

Setting these bits has no effect when executing at EL2, and it is the
OS's job to reason about how to configure lower exception levels.

So drop the initialization of CNTHCTL_EL2.

Signed-off-by: Ard Biesheuvel <ardb@kernel.org>

ArmPlatformPkg/PeilessSec/AArch64/ArchPeilessSec.c

@@ -21,12 +21,5 @@ ArchInitialize (
   if (ArmReadCurrentEL () == AARCH64_EL2) {
     // Trap General Exceptions. All exceptions that would be routed to EL1 are routed to EL2
     ArmWriteHcr (ARM_HCR_TGE);
-
-    /* Enable Timer access for non-secure EL1 and EL0
-       The cnthctl_el2 register bits are architecturally
-       UNKNOWN on reset.
-       Disable event stream as it is not in use at this stage
-    */
-    ArmWriteCntHctl (CNTHCTL_EL2_EL1PCTEN | CNTHCTL_EL2_EL1PCEN);
   }
 }

ArmPlatformPkg/Sec/AArch64/Helper.S

@@ -37,14 +37,6 @@ ASM_FUNC(SetupExceptionLevel2)
    mov     x1, #CPACR_DEFAULT
    csel    x0, x0, x1, eq
    msr     cptr_el2, x0           // Enable architectural features
-
-   // Enable Timer access for non-secure EL1 and EL0
-   // The cnthctl_el2 register bits are architecturally
-   // UNKNOWN on reset.
-   // Disable event stream as it is not in use at this stage
-   mov     x0, #(CNTHCTL_EL2_EL1PCTEN | CNTHCTL_EL2_EL1PCEN)
-   msr     cnthctl_el2, x0
-
    ret
 
 ASM_FUNCTION_REMOVE_IF_UNREFERENCED