c1e3e71643
Populate the gArmTransferListPpiGuid with the TransferList base address. Place the Ppi at the end of the PpiList For platforms with no TransferList support, boot continues without any errors. https://firmwarehandoff.github.io/firmware_handoff Signed-off-by: Prachotan Bathi <prachotan.bathi@arm.com>
279 lines
9.2 KiB
C
279 lines
9.2 KiB
C
/** @file
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Generic SEC driver for ARM platforms
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Copyright (c) 2011 - 2022, ARM Limited. All rights reserved.
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "Sec.h"
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/**
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This service of the EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI that migrates temporary
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RAM into permanent memory.
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@param PeiServices Pointer to the PEI Services Table.
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@param TemporaryMemoryBase Source Address in temporary memory from which
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the SEC or PEIM will copy the Temporary RAM
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contents.
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@param PermanentMemoryBase Destination Address in permanent memory into
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which the SEC or PEIM will copy the Temporary
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RAM contents.
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@param CopySize Amount of memory to migrate from temporary to
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permanent memory.
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@retval EFI_SUCCESS The data was successfully returned.
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@retval EFI_INVALID_PARAMETER PermanentMemoryBase + CopySize >
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TemporaryMemoryBase when TemporaryMemoryBase >
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PermanentMemoryBase.
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**/
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STATIC
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EFI_STATUS
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EFIAPI
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SecTemporaryRamSupport (
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IN CONST EFI_PEI_SERVICES **PeiServices,
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IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase,
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IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase,
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IN UINTN CopySize
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)
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{
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VOID *OldHeap;
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VOID *NewHeap;
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VOID *OldStack;
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VOID *NewStack;
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UINTN HeapSize;
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HeapSize = ALIGN_VALUE (CopySize / 2, CPU_STACK_ALIGNMENT);
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OldHeap = (VOID *)(UINTN)TemporaryMemoryBase;
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NewHeap = (VOID *)((UINTN)PermanentMemoryBase + (CopySize - HeapSize));
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OldStack = (VOID *)((UINTN)TemporaryMemoryBase + HeapSize);
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NewStack = (VOID *)(UINTN)PermanentMemoryBase;
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//
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// Migrate the temporary memory stack to permanent memory stack.
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//
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CopyMem (NewStack, OldStack, CopySize - HeapSize);
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//
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// Migrate the temporary memory heap to permanent memory heap.
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//
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CopyMem (NewHeap, OldHeap, HeapSize);
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SecSwitchStack ((UINTN)NewStack - (UINTN)OldStack);
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return EFI_SUCCESS;
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}
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STATIC CONST EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI mTemporaryRamSupportPpi = {
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SecTemporaryRamSupport
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};
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STATIC CONST EFI_PEI_PPI_DESCRIPTOR gCommonPpiTable[] = {
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{
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EFI_PEI_PPI_DESCRIPTOR_PPI,
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&gEfiTemporaryRamSupportPpiGuid,
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(VOID *)&mTemporaryRamSupportPpi
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}
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};
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/**
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Construct a PPI list from the PPIs provided in this file and the ones
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provided by the platform code.
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@param[out] PpiListSize Size of the PPI list in bytes
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@param[out] PpiList Pointer to the constructed PPI list
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@param[in] TransferListBase Pointer to the Transfer List base
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**/
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STATIC
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VOID
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CreatePpiList (
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OUT UINTN *PpiListSize,
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OUT EFI_PEI_PPI_DESCRIPTOR **PpiList,
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IN VOID *TransferListBase
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)
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{
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EFI_PEI_PPI_DESCRIPTOR *PlatformPpiList;
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UINTN PlatformPpiListSize;
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UINTN ListBase;
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EFI_PEI_PPI_DESCRIPTOR *LastPpi;
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// Get the Platform PPIs
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PlatformPpiListSize = 0;
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ArmPlatformGetPlatformPpiList (&PlatformPpiListSize, &PlatformPpiList);
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// Copy the Common and Platform PPis in Temporary Memory
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ListBase = PcdGet64 (PcdCPUCoresStackBase);
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CopyMem ((VOID *)ListBase, gCommonPpiTable, sizeof (gCommonPpiTable));
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CopyMem ((VOID *)(ListBase + sizeof (gCommonPpiTable)), PlatformPpiList, PlatformPpiListSize);
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// Set the Terminate flag on the last PPI entry
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LastPpi = (EFI_PEI_PPI_DESCRIPTOR *)ListBase +
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((sizeof (gCommonPpiTable) + PlatformPpiListSize) / sizeof (EFI_PEI_PPI_DESCRIPTOR)) - 1;
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*PpiListSize = sizeof (gCommonPpiTable) + PlatformPpiListSize;
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// Add the Transfer List PPI after the Common and Platform PPIs
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if (TransferListBase != NULL) {
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LastPpi++;
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LastPpi->Flags = EFI_PEI_PPI_DESCRIPTOR_PPI;
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LastPpi->Guid = &gArmTransferListPpiGuid;
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LastPpi->Ppi = TransferListBase;
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*PpiListSize += sizeof (EFI_PEI_PPI_DESCRIPTOR);
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}
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LastPpi->Flags |= EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;
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*PpiList = (EFI_PEI_PPI_DESCRIPTOR *)ListBase;
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}
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/**
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Prints firmware version and build time to serial console.
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**/
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STATIC
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VOID
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PrintFirmwareVersion (
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VOID
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)
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{
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CHAR8 Buffer[100];
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UINTN CharCount;
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CharCount = AsciiSPrint (
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Buffer,
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sizeof (Buffer),
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"UEFI firmware (version %s built at %a on %a)\n\r",
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(CHAR16 *)PcdGetPtr (PcdFirmwareVersionString),
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__TIME__,
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__DATE__
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);
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// Because we are directly bit banging the serial port instead of going through the DebugLib, we need to make sure
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// the serial port is initialized before we write to it
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SerialPortInitialize ();
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SerialPortWrite ((UINT8 *)Buffer, CharCount);
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}
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/**
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SEC main routine.
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@param[in] PeiCoreEntryPoint Address in ram of the entrypoint of the PEI
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core
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@param[in] TransferListBaseAddr Address of the Transfer List base address
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**/
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STATIC
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VOID
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EFIAPI
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SecMain (
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IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint,
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IN UINTN TransferListBaseAddr
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)
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{
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EFI_SEC_PEI_HAND_OFF SecCoreData;
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UINTN PpiListSize;
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EFI_PEI_PPI_DESCRIPTOR *PpiList;
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UINTN TemporaryRamBase;
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UINTN TemporaryRamSize;
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VOID *TransferListBase;
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// Dump the Transfer List
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TransferListBase = (VOID *)TransferListBaseAddr;
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if (TransferListBase != NULL) {
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if (TransferListCheckHeader (TransferListBase) != TRANSFER_LIST_OPS_INVALID) {
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DEBUG_CODE_BEGIN ();
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TransferListDump (TransferListBase);
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DEBUG_CODE_END ();
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} else {
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TransferListBase = NULL;
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DEBUG ((DEBUG_ERROR, "%a: No valid operations possible on TransferList found @ 0x%p\n", __func__, TransferListBase));
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}
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} else {
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DEBUG ((DEBUG_INFO, "%a: No TransferList found, continuing boot\n", __func__));
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}
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CreatePpiList (&PpiListSize, &PpiList, TransferListBase);
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// Adjust the Temporary Ram as the new Ppi List (Common + Platform Ppi Lists) is created at
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// the base of the primary core stack
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PpiListSize = ALIGN_VALUE (PpiListSize, CPU_STACK_ALIGNMENT);
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TemporaryRamBase = (UINTN)PcdGet64 (PcdCPUCoresStackBase) + PpiListSize;
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TemporaryRamSize = (UINTN)PcdGet32 (PcdCPUCorePrimaryStackSize) - PpiListSize;
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//
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// Bind this information into the SEC hand-off state
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// Note: this must be in sync with the stuff in the asm file
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// Note also: HOBs (pei temp ram) MUST be above stack
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//
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SecCoreData.DataSize = sizeof (EFI_SEC_PEI_HAND_OFF);
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SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet64 (PcdFvBaseAddress);
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SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdFvSize);
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SecCoreData.TemporaryRamBase = (VOID *)TemporaryRamBase; // We run on the primary core (and so we use the first stack)
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SecCoreData.TemporaryRamSize = TemporaryRamSize;
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SecCoreData.PeiTemporaryRamBase = SecCoreData.TemporaryRamBase;
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SecCoreData.PeiTemporaryRamSize = ALIGN_VALUE (SecCoreData.TemporaryRamSize / 2, CPU_STACK_ALIGNMENT);
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SecCoreData.StackBase = (VOID *)((UINTN)SecCoreData.TemporaryRamBase + SecCoreData.PeiTemporaryRamSize);
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SecCoreData.StackSize = (TemporaryRamBase + TemporaryRamSize) - (UINTN)SecCoreData.StackBase;
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// Jump to PEI core entry point
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(PeiCoreEntryPoint)(&SecCoreData, PpiList);
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}
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/**
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Module C entrypoint.
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@param[in] PeiCoreEntryPoint Address in ram of the entrypoint of the PEI
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core
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@param[in] TransferListBaseAddr Address of the Transfer List base address
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**/
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VOID
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CEntryPoint (
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IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint,
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IN UINTN TransferListBaseAddr
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)
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{
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if (!ArmMmuEnabled ()) {
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// Data Cache enabled on Primary core when MMU is enabled.
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ArmDisableDataCache ();
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// Invalidate instruction cache
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ArmInvalidateInstructionCache ();
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// Enable Instruction Caches on all cores.
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ArmEnableInstructionCache ();
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InvalidateDataCacheRange (
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(VOID *)(UINTN)PcdGet64 (PcdCPUCoresStackBase),
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PcdGet32 (PcdCPUCorePrimaryStackSize)
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);
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}
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// Write VBAR - The Exception Vector table must be aligned to its requirement
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// Note: The AArch64 Vector table must be 2k-byte aligned - if this assertion fails ensure
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// 'Align=4K' is defined into your FDF for this module.
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ASSERT (((UINTN)PeiVectorTable & ARM_VECTOR_TABLE_ALIGNMENT) == 0);
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ArmWriteVBar ((UINTN)PeiVectorTable);
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// Invoke "ProcessLibraryConstructorList" to have all library constructors
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// called.
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ProcessLibraryConstructorList ();
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PrintFirmwareVersion ();
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// Initialize the Debug Agent for Source Level Debugging
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InitializeDebugAgent (DEBUG_AGENT_INIT_POSTMEM_SEC, NULL, NULL);
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SaveAndSetDebugTimerInterrupt (TRUE);
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// Initialize the platform specific controllers
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ArmPlatformInitialize (ArmReadMpidr ());
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// Goto primary Main.
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SecMain (PeiCoreEntryPoint, TransferListBaseAddr);
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// PEI Core should always load and never return
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ASSERT (FALSE);
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}
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