GICv5 uses a different ID scheme for interrupt numbers to previous GICs; the
top bits indicate the type of interrupt (PPI/SPI/LPI). Update TimerDxe to use
the new ID scheme for GICv5. As the timer PPIs are architected for GICv5 they
should be the same on all GICv5 platforms.
Signed-off-by: Sarah Walker <Sarah.Walker2@arm.com>
Add initial driver support for GICv5. This initial driver supports Private
Peripheral Interrupts (PPIs) and Shared Peripheral Interrupts (SPIs).
Signed-off-by: Sarah Walker <Sarah.Walker2@arm.com>
[ardb: Merge v5 support into GicV3Dxe]
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Before extending the GicV3Dxe driver with support for GICv5, make the
driver AArch64-only to avoid the need for adding support to the 32-bit
build, which would be rather pointless.
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
The Universal Graphics Adapter (UGA) is a graphic abstraction.
The UGA I/O and Draw protocols are deprecated since UEFI 2.0 was
introduced. Cf. the UEFI spec v2.9:
"Appendix L - EFI 1.10 Protocol Changes and Deprecation List"
section L.2 "Deprecated Protocols"
Remove the UGA support.
Signed-off-by: GuoMinJ <newexplorerj@gmail.com>
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Move ArmMmuLib from ArmPkg to UefiCpuPkg for easy maintaining.
Continuous-integration-options: PatchCheck.ignore-multi-package
Signed-off-by: Ajan Zhong <ajan.zhong@newfw.com>
Since ArmMmuLib.h has been moved to UefiCpuPkg, add corresponding dec
file to AcceptableDependencies to ArmPkg, ArmPlatformPkg and ArmVirtPkg.
Continuous-integration-options: PatchCheck.ignore-multi-package
Signed-off-by: Ajan Zhong <ajan.zhong@newfw.com>
Move the ArmMmuLib interface definition to UefiCpuPkg, with this change,
MMU libraries for ARM, AARCH64, RiscV, LongArch64 architectures all
reside in UefiCpuPkg.
Continuous-integration-options: PatchCheck.ignore-multi-package
Signed-off-by: Ajan Zhong <ajan.zhong@newfw.com>
As the standalone MM core begins supporting MM Communicate v3, this
update extends its functionality to incorporate MM Communicate v3 headers
format, enabling compatibility with the new protocol.
Signed-off-by: Kun Qin <kun.qin@microsoft.com>
As the standalone MM core begins supporting MM Communicate v3, this
update extends its functionality to incorporate MM Communicate v3
headers, enabling compatibility with the new protocol.
Signed-off-by: Kun Qin <kun.qin@microsoft.com>
As MM cores start to support MM communciate v3. This change moves the
MM communicate driver to produce MM communicate v3 PPI.
Signed-off-by: Kun Qin <kun.qin@microsoft.com>
As MM cores start to support MM communciate v3. This change moves the
MM communicate driver to produce MM communicate v3 protocol.
Signed-off-by: Kun Qin <kun.qin@microsoft.com>
Now that the use of 18 registers for FF-A is supported. Registers
from x0-x17 can be used by FF-A to return call results. StMM also uses
registers x19-x23 to store SPMC boot information.
Use the x24 register to store the stack address instead of x12
to avoid it being clobbered by FF-A calls.
Signed-off-by: Mohamed Gamal Morsy <mohamed.morsy@arm.com>
To get a SPI_MAX_INTID, interrupt controller type Register
should be masked with ARM_GIC_ICDICTR_GET_SPI_RANGE.
However, since ARM_GIC_ICDICTR_SPI_RANGE_TO_MAX_INTID macro
uses ARM_GIC_ICDICTR_GET_EXT_SPI_RANGE mask,
it returns wrong SPI_MAX_INITID.
This makes a failure of loading GenericWatchDog in FVP RevC model.
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
Fixes: d6d2f68e38 ("ArmPkg/Drivers/ArmGicDxe: ...")
As new interfaces are made available to support UUID-GUID conversion,
this change is made to leverage new interfaces and remove the locally
duplicated code.
Signed-off-by: Kun Qin <kun.qin@microsoft.com>
This commit enables extended SPI support for GicV3. GicV3 must decide,
based on the source intid, whether to access the SPI-range registers,
PPI-range registers in the redistributor, or the extended SPI-range
registers.
The protocol interfaces must also support registering an interrupt
handler with an extended SPI intid. To save ~24KB of memory, handler
allocation and access is delegated to GicV2 and GicV3. GicV2 retains the
existing handler mapping scheme using intids literally. GicV3 remaps
extended SPI intids to be immediately after the highest SPI intids.
Tested on qemu with the BSA test suite.
Signed-off-by: Nick Graves <nicholasgraves@google.com>
ArmStandaloneMmCoreEntryPoint makes use of GetNextHob
which comes from HobLib. The inf does not specify
HobLib has one of its library classes. Specify
HobLib in the LibraryClasses section of the
inf.
Signed-off-by: Aaron Pop <aaronpop@microsoft.com>
The current warm reset implementation attempts the PSCI SYSTEM_RESET2
command twice without clearing the local variable used for Arg1. This can
result in passing a random value as the reset type, which may cause the
PSCI call to behave unexpectedly and fall back to a cold reset.
This change addresses the issue by:
- Correcting the monitor call function ID.
- Explicitly zeroing the reset type field before invoking the PSCI
interface.
The updated warm reset flow has been tested and confirmed to invoke
SYSTEM_RESET2 as expected.
Signed-off-by: Kun Qin <kun.qin@microsoft.com>
MessageParams1 and MessageParams2 always point to adjacent slots in the
payload buffer, so no need to keep two separate pointers.
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Fix an issue where input parameters in SCMI messages may be overwritten by
return values during repeated transactions when retrieving large data sets.
This issue affects:
1. ClockDescribeRates: when the number of clock rates exceeds the transfer
limit. According to the SCMI specification (Section 4.6.2.5), the first
and second parameters are initially used to pass clock_id and rate_index.
However, due to SCMI’s shared memory communication mechanism, these same
memory locations are later reused to return status and num_rate_flags.
2. PerformanceDescribeLevels: when the number of performance levels is too
large to return in a single response. As described in Section 4.5.3.5,
the first and second parameters are initially used for domain_id and
level_index, but are overwritten with status and num_levels in the return.
Because SCMI reuses the same shared memory buffer for both input and output,
the return values can override input parameters if the buffer is not properly
re-initialized before each request. This patch ensures that the first and
second parameters are correctly set before every transaction to preserve
input integrity and ensure correct protocol behavior.
Signed-off-by: jie.fu <jie.fu@cixtech.com>
AArch64 no longer uses PcdVFPEnabled, so make the definition ARM-specific
and stop explicitly setting it for AArch64 platforms.
Continuous-integration-options: PatchCheck.ignore-multi-package
Signed-off-by: Leif Lindholm <leif.lindholm@oss.qualcomm.com>
CpuDxe no longer uses PcdVFPEnabled, so drop the dependency
declaration before turning that Pcd ARM-only.
Signed-off-by: Leif Lindholm <leif.lindholm@oss.qualcomm.com>
ArmFfaLib is an implementation of an industry specification-defined
interface with UEFI specific method of handling Rx/Tx buffer sharing
across multiple boot phases, which is more appropriately placed in
MdeModulePkg.
This update relocates the implementation of ArmFfaLib to MdeModulePkg,
thereby supporting the FFA call primitives for all other packages that
depend on this interface.
Continuous-integration-options: PatchCheck.ignore-multi-package
Signed-off-by: Kun Qin <kun.qin@microsoft.com>
As a set of definitions from an industry specification-defined interface,
ArmFfaLib.h is more appropriately placed in MdePkg.
This update relocates both the header definition of ArmFfaLib to MdePkg,
thereby supporting the monitor call primitives for all other packages
that depend on this interface.
Continuous-integration-options: PatchCheck.ignore-multi-package
Signed-off-by: Kun Qin <kun.qin@microsoft.com>
As an implementation of an industry specification-defined interface,
ArmSvcLib is more appropriately placed in MdePkg.
This update relocates both the header definition and the implementation
of ArmSvcLib to MdePkg, thereby supporting the supervisor call primitives
for all other packages that depend on this interface.
Continuous-integration-options: PatchCheck.ignore-multi-package
Signed-off-by: Kun Qin <kun.qin@microsoft.com>
ArmSmcLibNull is a null implementation of an industry specification-
defined interface, which is defined in MdePkg.
This update relocates the null implementation of ArmSmcLib to MdePkg,
thereby supporting the monitor call primitives for ARM platforms that
does not have SMC capabilities.
Continuous-integration-options: PatchCheck.ignore-multi-package
Signed-off-by: Kun Qin <kun.qin@microsoft.com>
As an implementation of an industry specification-defined interface,
ArmSmcLib is more appropriately placed in MdePkg.
This update relocates both the header definition and the implementation
of ArmSmcLib to MdePkg, thereby supporting the monitor call primitives
for all other packages that depend on this interface.
Continuous-integration-options: PatchCheck.ignore-multi-package
Signed-off-by: Kun Qin <kun.qin@microsoft.com>
ArmFfaBootInfo.h, ArmFfaPartInfo.h and ArmFfaSvc.h comprise a set of
definitions established by industry standard specifications:
https://developer.arm.com/documentation/den0077/latest
This update relocates the header definitions from ArmPkg to MdePkg to
maintain consistency within the EDK2 layout.
Continuous-integration-options: PatchCheck.ignore-multi-package
Signed-off-by: Kun Qin <kun.qin@microsoft.com>
ArmStdSmc.h comprises a set of definitions established by an industry
standard specification:
https://developer.arm.com/documentation/den0028/latest/
This update relocates the header definition from ArmPkg to MdePkg to
maintain consistency within the EDK2 repo layout.
Continuous-integration-options: PatchCheck.ignore-multi-package
Signed-off-by: Kun Qin <kun.qin@microsoft.com>
This change added the support for using 18 registers when FF-A
DIRECT_REQ2 is used to communicate with MM core.
This change was tested on QEMU SBSA and booted to Windows.
Signed-off-by: Kun Qin <kun.qin@microsoft.com>
This change expands the support of FF-A direct message 2 call to use the
full 18 registers.
It also adds a check in the contructors to ensure the SMCCC meets the
minimal requirement of v1.2 to support FF-A v1.2 usage.
Signed-off-by: Kun Qin <kun.qin@microsoft.com>
This extends ARM_SVC_ARGS to support all x0-x17 registers use case for
FF-A.
The ArmCallSvc function is also updated to support 18-register usage.
Co-authored-by: Olivier Deprez <Olivier.Deprez@arm.com>
Signed-off-by: Kun Qin <kun.qin@microsoft.com>
This extends ARM_SMC_ARGS to support all x0-x17 registers use case for
FF-A.
The ArmCallSmc function is also updated to support 18-register usage.
Signed-off-by: Kun Qin <kun.qin@microsoft.com>
Add and install a protocol notification handler for
gEfiDxeMmReadyToLockProtocolGuid, in order to to trigger MMI
handler to install gEfiMmReadyToLockProtocolGuid protocol in Mm.
Signed-off-by: Crystal Lee <CrystalLee@ami.com>
The existing code was full of abbreviated function/variable names.
Let's nip that in the bud before we add more code to this library.
Update the current only upstream user: ArmStandaloneMmCoreEntryPoint.
Signed-off-by: Leif Lindholm <leif.lindholm@oss.qualcomm.com>
This change added missing FF-A definitions for certain FF-A function IDs.
The `ARM_FFA_NOTIFICATION_*` and `ARM_FFA_FEATURE_*` definitions are
based on FF-A spec v1.3 ALP1.
The `ARM_FFA_MEM_PERM_RESERVED_MASK` definition is based on FF-A memory
protocol spec v1.3 ALP1.
Signed-off-by: Kun Qin <kun.qin@microsoft.com>
Compilation error:
```
ArmStandaloneMmCoreEntryPoint.c:1041:48: error: cast to smaller
integer type 'unsigned long' from 'void *'
[-Werror,-Wvoid-pointer-to-int-cast]
1041 | DEBUG ((DEBUG_INFO, "Start Dump Hob: %lx\n",
(unsigned long)HobStart));
```
The `%p` specifer is now used to print the pointers.
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
ArmFfaLibCommonInit will return EFI_UNSUPPORTED when there is no FFA
supported on the platform. This is expected behavior. However, the return
of error code will incur program asserts.
This change fixed the non-FFA path for the Standalone MM instance.
Signed-off-by: Kun Qin <kun.qin@microsoft.com>
This commit oves StackCheckLib from a NULL lib to an instance of
StackCheckLib. This requires every entry point to add a library
dependency on StackCheckLib. It also requires every SEC module
to have a dependency on StackCheckLib because there is no
standard SEC entry point.
It allows for greater flexibility for a platform to apply stack
cookies and simplifies DSC logic.
Continuous-integration-options: PatchCheck.ignore-multi-package
Signed-off-by: Oliver Smith-Denny <osde@microsoft.com>
ArmDisassemblerLib is used to pretty print the instruction that
triggered an unhandled exception, but it was never implemented for
AARCH64, and according to the existing file comment, Thumb2 support
(which is used predominantly when building EDK2 for 32-bit ARM due to
its smaller size) is incomplete.
The DEBUG diagnostics that are produced on an unhandled exception are
generally sufficient to dump the entire executable that triggered it,
and so this disassembly is of limited value, especially because it
doesn't work on AARCH64.
So let's start getting rid of it, by dropping references to it in code
and in the various .INF and .DSC files. Once out-of-tree platforms have
been allowed to catch up, we can remove the library implementation and
its class definition entirely.
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
There were several bugs in the vector table relocation code which means
it can't really have been used by anyone on AArch64 in the last decade or
so. So delete the support code from the library, as well as the
ArmRelocateExceptionLib.inf file.
This gets rid of PcdDebuggerExceptionSupport (including a duff reference
in CpuDxe), PcdCpuVectorBaseAddress and PcdRelocateVectorTable.
Signed-off-by: Leif Lindholm <leif.lindholm@oss.qualcomm.com>
The GIC driver itself has intimate knowledge of the hardware, and so it
is the best suited to create the mappings of the MMIO control regions,
in case they have not been mapped yet by the platform code.
So call in the the CPU arch protocol to map the CPU interface,
distributor and redistributor regions as they are discovered by the GIC
driver startup code.
Note that creating these mappings has no effect if the regions in
question have already been mapped with the correct attributes.
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
The GIC distributor and redistributor addresses that are passed into the
interrupt enable and disable routines are always the same, so just use
the global variables directly.
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
The GIC DXE driver only runs on the boot CPU, and so there is really no
point in iterating over all the redistributor frames every time an
interrupt is enabled, disabled or its state tested. Instead, do this
only at load time.
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Instead of relying on a protocol notification event to register the core IRQ
interrupt handler with CPU arch protocol once it becomes available, use
a DEPEX to ensure that the GIC driver is not dispatched at all until the
CPU arch protocol has turned up.
This will allow the GIC driver to use other CPU arch protocol methods,
such as the ones needed to map the GIC MMIO regions at driver startup.
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Currently, ArmPkg's CpuDxe DEPEXes on the hardware interrupt protocol,
to ensure that it is not dispatched before the GIC driver. This way, the
CpuDxe driver is guaranteed not to enable interrupts on the CPU side
before the GIC driver has had the opportunity to configure the
interrupts on the distribution side.
However, this prevents the GIC driver from using any of the CPU arch
protocol interfaces, such as mapping memory, which it may need to do on
platforms where the GIC MMIO regions are not mapped yet when the driver
is started.
So instead, use a protocol notification on the hardware interrupt
protocol, which is installed by the GIC driver (as well as other
existing interrupt controller drivers for platforms that do not
implement a GIC) after it starts up and deasserts and disables all
incoming interrupts. Manipulate the interrupt state as usual only after
this notification has been received. Before that, keep track of the
caller's intent regarding the interrupt enabled state in a shadow
variable, but do not actually enable interrupt delivery to the CPU just
yet.
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
