diff --git a/ArmPlatformPkg/Sec/AArch64/Helper.S b/ArmPlatformPkg/Sec/AArch64/Helper.S
index 121f99838c..578c41e0bb 100644
--- a/ArmPlatformPkg/Sec/AArch64/Helper.S
+++ b/ArmPlatformPkg/Sec/AArch64/Helper.S
@@ -12,8 +12,8 @@
 ASM_FUNC(SetupExceptionLevel1)
    mov  x5, x30                   // Save LR
 
-   mov  x0, #CPACR_CP_FULL_ACCESS
-   bl   ASM_PFX(ArmWriteCpacr)    // Disable copro traps to EL1
+   mov  x0, #CPACR_DEFAULT
+   bl   ASM_PFX(ArmWriteCpacr)    // Enable architectural features
 
    ret  x5
 
@@ -30,7 +30,7 @@ ASM_FUNC(SetupExceptionLevel2)
 
    // NB: We assume that we have not been entered on VHE systems with
    // HCR_EL2.E2H set.
-   msr     cptr_el2, xzr          // Disable copro traps to EL2
+   msr     cptr_el2, xzr          // Enable architectural features
 
    // Enable Timer access for non-secure EL1 and EL0
    // The cnthctl_el2 register bits are architecturally
diff --git a/MdePkg/Include/AArch64/AArch64.h b/MdePkg/Include/AArch64/AArch64.h
index c1a24c1e30..3186bfb548 100644
--- a/MdePkg/Include/AArch64/AArch64.h
+++ b/MdePkg/Include/AArch64/AArch64.h
@@ -16,10 +16,10 @@
 #define ARM_ARCH_EXCEPTION_IRQ  EXCEPT_AARCH64_IRQ
 
 // CPACR - Coprocessor Access Control Register definitions
-#define CPACR_TTA_EN          (1UL << 28)
-#define CPACR_FPEN_EL1        (1UL << 20)
-#define CPACR_FPEN_FULL       (3UL << 20)
-#define CPACR_CP_FULL_ACCESS  0x300000
+#define CPACR_TTA_EN     (1UL << 28)
+#define CPACR_FPEN_EL1   (1UL << 20)
+#define CPACR_FPEN_FULL  (3UL << 20)
+#define CPACR_DEFAULT    CPACR_FPEN_FULL
 
 // Coprocessor Trap Register (CPTR)
 #define AARCH64_CPTR_TFP  (1 << 10)