Mirocom/EDK2-fork
1
0
Fork 0
Code Issues Pull Requests Actions 2 Packages Projects Releases Wiki Activity

IntelFsp2Pkg: Preserve GDTR and CS/DS/ES/FS/GS/SS

Browse Source 
Bootloader does not expect FSP modifies GDTR and segment selectors, update
FSP entry/exit code to preserve these registers.

Signed-off-by: Ray Ni <ray.ni@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Cc: Ted Kuo <ted.kuo@intel.com>
Cc: Ashraf Ali S <ashraf.ali.s@intel.com>
This commit is contained in:
Ray Ni
2025-07-15 15:41:50 +08:00
committed by mergify[bot]
parent 8be9a344d3
commit 562bce0feb
4 changed files with 81 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

20
IntelFsp2Pkg/FspSecCore/X64/Fsp24ApiEntryM.nasm
View File

@@ -1,7 +1,7 @@
;; @file
; Provide FSP API entry points.
;
; Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
; Copyright (c) 2022 - 2025, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent
;;
DEFAULT REL
@@ -173,6 +173,24 @@ NotMultiPhaseMemoryInitApi:
push rdx
SkipPagetableSave:
; Save Segment registers
mov rdx, ss
push rdx
mov rdx, gs
push rdx
mov rdx, fs
push rdx
mov rdx, es
push rdx
mov rdx, ds
push rdx
mov rdx, cs
push rdx
; Reserve 16 bytes for GDT save/restore
sub rsp, 16
sgdt [rsp]
; Reserve 16 bytes for IDT save/restore
sub rsp, 16
sidt [rsp]

20
IntelFsp2Pkg/FspSecCore/X64/FspApiEntryM.nasm
View File

@@ -1,7 +1,7 @@
;; @file
; Provide FSP API entry points.
;
; Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
; Copyright (c) 2022 - 2025, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent
;;
DEFAULT REL
@@ -141,6 +141,24 @@ ASM_PFX(FspApiCommonContinue):
push rdx
SkipPagetableSave:
; Save Segment registers
mov rdx, ss
push rdx
mov rdx, gs
push rdx
mov rdx, fs
push rdx
mov rdx, es
push rdx
mov rdx, ds
push rdx
mov rdx, cs
push rdx
; Reserve 16 bytes for GDT save/restore
sub rsp, 16
sgdt [rsp]
; Reserve 16 bytes for IDT save/restore
sub rsp, 16
sidt [rsp]

4
IntelFsp2Pkg/Library/BaseFspCommonLib/FspCommonLib.c
View File

@@ -31,7 +31,9 @@ typedef struct {
} CONTEXT_STACK;
typedef struct {
UINT64 Idtr[2]; // IDTR Limit - bit0:bi15, IDTR Base - bit16:bit79
UINT64 Idtr[2]; // IDTR Limit - bit0:bit15, IDTR Base - bit16:bit79
UINT64 Gdtr[2]; // GDTR Limit - bit0:bit15, GDTR Base - bit16:bit79
UINT64 Segment[6]; // Segment Registers: CS, DS, ES, FS, GS, SS
UINT64 Cr0;
UINT64 Cr3;
UINT64 Cr4;

41
IntelFsp2Pkg/Library/BaseFspSwitchStackLib/X64/Stack.nasm
View File

@@ -1,6 +1,6 @@
;------------------------------------------------------------------------------
;
; Copyright (c) 2022 - 2023, Intel Corporation. All rights reserved.<BR>
; Copyright (c) 2022 - 2025, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
; Abstract:
@@ -92,6 +92,25 @@ ASM_PFX(FspSwitchStack):
push rdx
SkipPagetableSave:
; Save Segment registers
mov rdx, ss
push rdx
mov rdx, gs
push rdx
mov rdx, fs
push rdx
mov rdx, es
push rdx
mov rdx, ds
push rdx
mov rdx, cs
push rdx
; Reserve 16 bytes for GDT save/restore
sub rsp, 16
sgdt [rsp]
; Reserve 16 bytes for IDT save/restore
sub rsp, 16
sidt [rsp]
@@ -106,6 +125,26 @@ SkipPagetableSave:
lidt [rsp]
add rsp, 16
; Restore GDTR
lgdt [rsp]
add rsp, 16
; Restore Segment registers
lea rdx, [.0]
push rdx ; Push return address
retfq ; Far return to restore CS (uses CS from stack + return address)
.0:
pop rdx
mov ds, dx
pop rdx
mov es, dx
pop rdx
mov fs, dx
pop rdx
mov gs, dx
pop rdx
mov ss, dx
lea rax, [ASM_PFX(FeaturePcdGet (PcdFspSaveRestorePageTableEnable))]
mov al, byte [rax]
cmp al, 0